The present invention relates to signal generation, and more particularly to a method of digital fine delay processing to produce a delayed analog signal from a digital signal representative of an undelayed analog signal with greater than one clock cycle resolution.
Digital technology has been developing, and information that used to be stored in analog form is now stored in digital form. However, eventually the digital data is converted into an analog signal when it is displayed, for example. An electronic circuit sometimes requires delaying an analog signal. It is easy to provide a delay equal to an integer multiple of a clock cycle, but often higher resolution is required.
FIG. 1 shows a conventional delay circuit for providing a high-resolution delay to an analog signal produced from digital data to produce a delayed analog signal. A data generator 10, which may be a storage unit such as a hard disk drive or a receiver for terrestrial digital broadcasting, provides N-bit digital data at a rate determined by a reference clock CLK. The N-bit digital data is converted into an analog signal by a digital-to-analog converter (DAC) 12 using the reference clock CLK. An analog delay line 14 delays the analog signal from the DAC 12 according to a delay control signal that determines in a continuous manner the amount of delay inserted by the analog delay line. This approach provides a delay having a resolution greater than one cycle of the reference clock CLK. The delay in the circuit shown in FIG. 1 does not always have a linear relationship to the delay control signal, so it is difficult to precisely control the delay amount. The analog signal is itself delayed, which degrades the delayed analog signal quality. Also a typical analog delay line 14 generates such heat that it is not suitable as part of an integrated circuit.
FIG. 2 shows another conventional delay circuit that controls the delay of the analog signal by delaying the reference clock CLK that is provided to the digital-to-analog converter (DAC) 12. The analog delay circuit 16 delays the reference clock CLK to provide a delayed clock DCLK that is provided to the DAC 12 to convert the N-bit digital data into the delayed analog signal. The delay of the reference clock CLK in the analog delay circuit 16 also is controlled by the delay control signal similar to the example of FIG. 1.
As shown in FIG. 3, analog signal 30 is the output signal from the DAC 12 when there is no delay in the delayed clock DCLK relative to the reference clock CLK, and analog signal 32 is a delayed version of analog signal 30 when there is a delay of Δt in the delayed clock DCLK. Sample points in the analog signals 30 and 32 represent the sample values of the corresponding digital data. The delay Δt of the delayed clock DCLK provided to the DAC 12 relative to the reference clock CLK is equivalent to the delays of the sample points of the digital data for the analog signal 30 being shifted horizontally in the delayed analog signal 32. Thus the delay Δt is smaller than the cycle of the reference clock CLK.
The circuit shown in FIG. 2 has the same problems due to the analog delay circuit 16 as that of FIG. 1. The reference clock for the digital data and the delayed clock for the DAC 12 are different so that a timing margin may become critical in the digital-to-analog conversion process of the DAC 12 if the delay Δt is too large. To avoid this situation, delay lines may be inserted into the respective N-bit data lines, which requires that the number of the delay lines equals the number of bits—N. As described above, an analog delay line has many issues. Other issues include sensitivity to temperature variation or tolerance variability of parts so that it is difficult to obtain a stable characteristic.
Since it is difficult for the analog delay circuit 16 to control the delay accurately, a digital delay line may be used for accurate delay control of an analog signal. For example, U.S. Pat. No. 6,218,880 (Relph) discloses technology that converts an analog input signal into parallel digital data with each bit being delayed by a separate digital delay line, and then reconverts the outputs from the multiple digital delay lines into an analog signal to provide a desired delay for the analog input signal. The delay of the Relph circuit, however, provides only delays that are integer multiples of the cycle of the clock, i.e., does not provide a continuous delay that is smaller than the clock cycle.
What is desired is a method of generating a continuous delay over a range of less than one clock cycle to provide a high resolution delay for an analog signal produced from digital data.